The present disclosure relates to memory device command-address-control, and more specifically, to calibration of memory device command-address-control.
Engineers encounter memory test and simulation idiosyncrasies while designing, testing and validating the memory communication bus of memory devices because of variations in hardware that may cause testing models to inaccurately reflect the hardware. Memory controller bus timing values are commonly refined periodically for proper operation and margin across a large sample of hardware, which is both labor intensive and time consuming. Each time the memory controller bus timing values are refined or modified, or the hardware is modified, the validation process must be repeated and re-tested for the new settings and/or hardware.
More particularly, current memory calibration and validation systems may not dynamically calibrate the command-address-control nets at the device level relative to their reference voltage supplied by the controller. This may lead to memory performance for the devices being sub-optimal and not completely reliable. Moreover, current systems do not perform dynamic calibration of command-address-control nets at device initialization and do not provide the option of being periodically adjusted during device runtime. Accordingly, they do not allow the best possible values for each device on the command-address-control flyby to calibrate itself for the most optimal setup, hold, and reference voltage settings for optimal device operation. Calibration does not run automatically at power on and requires an initial passing setting. These development limitations may lead to overall signal-integrity problems for some memory designs